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Lattice Semiconductor
Detailed Register Descriptions
(0x)
CSIX-to-PI40 IP Core User’s Guide
Absolute
Reset Value
Address
Bit
Name
(0x)
Description
Global Control Register (Read/Write)
8000
[0:3]
[4]
Not Used
Reset_Enable
01
Not Used
When high, this bit initializes all registers and resets all trans-
mission logic. Note that this reset function is self clearing.
[5]
[6]
[7]
H_Parity_Enable
V_Parity_Enable
Transmission_Enable
When high, horizontal parity error detectors on inbound CSIX
ports are enabled to operate for all instantiated channels.
When high, vertical parity error detectors on inbound CSIX
ports are enabled to operate for all instantiated channels.
When high, CSIX transmission logic is enabled to operate for
all instantiated channels.
Reset Control Register (Read/Write)
8004
[0:5]
[6]
Not Used
Reset_1
00
Not Used
When high, transmission logic for channel 1 is reset. Note this
bit is not self clearing. The bit must be written to “0” to deas-
sert the associated reset.
[7]
Reset_0
When high, transmission logic for channel 0 is reset. Note this
bit is not self clearing. The bit must be written to “0” to deas-
sert the associated reset.
FIFO Flush Register (Read/Write)
8008
[0:5]
[6]
Not Used
Flush_1
00
Not Used
When high, all FIFOs for channel 1 are ?ushed. Note this bit is
not self clearing. The bit must be written to “0” to deassert the
associated ?ush.
[7]
Flush_0
When high, all FIFOs for channel 0 are ?ushed. Note this bit is
not self clearing. The bit must be written to “0” to deassert the
associated ?ush.
Force H Parity Error Registration (Read/Write)
800C
[0:5]
[6]
Not Used
Force HPERR_1
00
Not Used
When high, the horizontal parity checker on channel 1 is
forced to detect a parity error. Note this bit is not self clearing.
The bit must be written to “0” to deassert the associated error
condition.
[7]
Force HPERR_0
When high, the horizontal parity checker on channel 0 is
forced to detect a parity error. Note this bit is not self clearing.
The bit must be written to “0” to deassert the associated error
condition.
Force V Parity Error Registration (Read/Write)
8010
[0:5]
[6]
Not Used
Force VPERR_1
00
Not Used
When high, the vertical parity checker on channel 0 is forced
to detect a parity error. Note this bit is not self clearing. The bit
must be written to “0” to deassert the associated error condi-
tion.
[7]
Force VPERR_0
When high, the vertical parity checker on channel 1 is forced
to detect a parity error. Note this bit is not self clearing. The bit
must be written to “0” to deassert the associated error condi-
tion.
13
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